Title :
Yield and speed optimization of a latch-type voltage sense amplifier
Author :
Wicht, Bernhard ; Nirschl, Thomas ; Schmitt-Landsiedel, Doris
Author_Institution :
Mixed-Signal Power & Control, Texas Instruments Deutschland GmbH, Freising, Germany
fDate :
7/1/2004 12:00:00 AM
Abstract :
A quantitative yield analysis of a latch-type voltage sense amplifier with a high-impedance differential input stage is presented. It investigates the impact of supply voltage, input DC level, transistor sizing, and temperature on the input offset voltage. The input DC level turns out to be most significant. Also, an analytical expression for the sensing delay is derived which shows low sensitivity on the input DC bias voltage. A figure of merit indicates that an input dc level of 0.7 VDD is optimal regarding speed and yield. Experimental results in 130-nm CMOS technology confirm that the yield can be significantly improved by lowering the input DC voltage to about 70% of the supply voltage. Thereby, the offset standard deviation decreases from 19 to 8.5 mV without affecting the delay.
Keywords :
CMOS integrated circuits; amplifiers; differential amplifiers; electric impedance; optimisation; 130 nm; 19 to 8.5 mV; CMOS technology; SRAM circuits; SRAM yield; current sensing; high-impedance differential input stage; input DC bias voltage; input DC level; input offset voltage; latch delay; latch-type voltage sense amplifier; quantitative yield analysis; sensing delay; speed optimization; supply voltage; transistor sizing; yield optimization; CMOS technology; Circuit noise; Delay; Differential amplifiers; Feedback; Flip-flops; Latches; Random access memory; Temperature sensors; Voltage; Current sensing; SRAM circuits; SRAM yield; latch delay; latch-type sense amplifier; sense amplifier; yield optimization;
Journal_Title :
Solid-State Circuits, IEEE Journal of
DOI :
10.1109/JSSC.2004.829399
