A 30-ns 64-Mb DRAM with built-in self-test and self-repair function

Author

Tanabe, Akira ; Takeshima, Toshio ; Koike, Hiroki ; Aimoto, Yoshiharu ; Takada, Masahide ; Ishijima, Toshiyuki ; Kasai, Naoki ; Hada, Hiromitsu ; Shibahara, Kentaro ; Kunio, Takemitsu ; Tanigawa, Takaho ; Saeki, Takanori ; Sakao, Masato ; Miyamoto, Hideno

Author_Institution

NEC Corp., Kanagawa, Japan

Volume

27

Issue

11

fYear

1992

fDate

11/1/1992 12:00:00 AM

Firstpage

1525

Lastpage

1533

Abstract

A 64-Mb dynamic random access memory (DRAM) with a 30-ns access time and 19.48-mm×9.55-mm die size has been developed. For reducing inter-bit-line coupling noise, the DRAM features a latched-sense, shared-sense circuit with open bit-line readout and folded bit-line rewrite operations. To reduce test costs and increase chip reliability, it has been equipped with built-in self-test and self-repair (BIST and BISR) circuits that use spare SRAM cells

Keywords

CMOS integrated circuits; DRAM chips; built-in self test; integrated circuit testing; 30 ns; 64 Mbit; BIST; DRAM; built-in self-test; chip reliability; dynamic RAM; dynamic random access memory; folded bit-line rewrite operations; inter-bit-line coupling noise; latched sense circuit; noise reduction; open bit-line readout; self-repair function; shared-sense circuit; spare SRAM cells; triple-well CMOS process; Automatic testing; Built-in self-test; Circuit noise; Circuit testing; Coupling circuits; Error correction codes; Noise level; Noise reduction; Random access memory; Voltage;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.165332

Filename

165332