A 50-ns 256 K CMOS split-gate EPROM

Author

Ali, Syed B. ; Sani, Bramak ; Shubat, Alex S. ; Sinai, Keyhan ; Kazerounian, Reza ; Hu, Ching-Jen ; Ma, Yueh Yale ; Eitan, Boaz

Author_Institution

WaferScale Integration Inc., Fremont, CA, USA

Volume

23

Issue

1

fYear

1988

Firstpage

79

Lastpage

85

Abstract

A high-speed 32 K*8 CMOS EPROM has been designed and implemented in a polycide 1.2- mu m n-well epi CMOS technology. A high-read-current split-gate EPROM cell combined with address transition detection-based SRAM-like precharge, equalization, and clocked differential sensing schemes has resulted in a typical address access time of less than 50 ns. The typical power dissipation at 18.2 MHz is 60 mW. Row redundancy is used to enhance the yield and the part has been designed to be compatible with plastic packaging.<>

Keywords

CMOS integrated circuits; PROM; integrated memory circuits; redundancy; 1.2 micron; 18.2 MHz; 256 kbit; 50 ns; 60 mW; CMOS; address access time; address transition detection based precharge; clocked differential sensing schemes; equalization; high-read-current; high-speed; plastic packaging; polycide n-well epi technology; power dissipation; row redundancy; split-gate EPROM; Channel hot electron injection; Circuit synthesis; Current measurement; EPROM; Electric breakdown; Equivalent circuits; MOS devices; MOSFETs; Nonvolatile memory; Split gate flash memory cells;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.260

Filename

260