A 200-MHz 64-b dual-issue CMOS microprocessor

Author

Dobberpuhl, Daniel W. ; Witek, Richard T. ; Allmon, Randy ; Anglin, Robert ; Bertucci, David ; Britton, Sharon ; Chao, Linda ; Conrad, Robert A. ; Dever, Daniel E. ; Gieseke, Bruce ; Hassoun, Soha M N ; Hoeppner, Gregory W. ; Kuchler, Kathryn ; Ladd, Maur

Author_Institution

Digital Equipment Corp., Hudson, MA, USA

Volume

27

Issue

11

fYear

1992

fDate

11/1/1992 12:00:00 AM

Firstpage

1555

Lastpage

1567

Abstract

A 400-MIPS/200-MFLOPS (peak) custom 64-b VLSI CPU is described. The chip is fabricated in a 0.75-μm CMOS technology utilizing three levels of metalization and optimized for 3.3-V operation. The die size is 16.8 mm×13.9 mm and contains 1.68 M transistors. The chip includes separate 8-kbyte instruction and data caches and a fully pipelined floating-point unit (FPU) that can handle both IEEE and VAX standard floating-point data types. It is designed to execute two instructions per cycle among scoreboarded integer, floating-point, address, and branch execution units. Power dissipation is 30 W at 200-MHz operation

Keywords

CMOS integrated circuits; VLSI; microprocessor chips; pipeline processing; 0.75 micron; 200 MFLOPS; 200 MHz; 3.3 V; 30 W; 400 MIPS; 64 bit; CMOS microprocessor; IEEE standard; VAX standard; address units; branch execution units; custom VLSI CPU; dual issue type; floating-point data types; fully pipelined floating-point unit; scoreboarded integer; CMOS process; CMOS technology; Chaos; Clocks; Microprocessors; Pins; Power dissipation; Registers; Very large scale integration; Wires;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.165336

Filename

165336