Title :
A 100-MHz macropipelined VAX microprocessor
Author :
Badeau, Roy W. ; Bahar, R. Iris ; Bernstein, Debra ; Biro, Larry L. ; Bowhill, William J. ; Brown, John F. ; Case, Michael A. ; Castelino, Ruben W. ; Cooper, Elizabeth M. ; Delaney, Maureen A. ; Deverell, David R. ; Edmonson, J.H. ; Ellis, John J. ; Fisch
Author_Institution :
Digital Equipment Corp., Hudson, MA, USA
fDate :
11/1/1992 12:00:00 AM
Abstract :
A macropipelined CISC microprocessor was implemented in a 0.75-μm CMOS 3.3-V technology. The 1.3-million-transistor custom chip measures 1.62×1.46 cm2 and dissipates 16.3 W. The 100-MHz parts were benchmarked at 50 SPEC marks. The on-chip clocking system and several high-performance logic and circuit techniques are described. Macroinstruction handling, micropipeline management, and control store structures highlight the design architecture. The hierarchical array organization and fast tag comparison technique of the primary cache are discussed. Power estimation procedures are outlined, and the results are compared to measurements. Physical design and verification methods, and CAD tools are also described. After extensive functional verification efforts are described, chip and system test results are presented
Keywords :
CMOS integrated circuits; microprocessor chips; pipeline processing; 0.75 micron; 100 MHz; 16.3 W; 3.3 V; CAD tools; CISC microprocessor; CMOS; architecture; control store; custom chip; fast tag comparison technique; functional verification; hierarchical array organization; macroinstruction handling; macropipelined VAX microprocessor; micropipeline management; on-chip clocking system; power estimation procedures; primary cache; verification methods; CMOS logic circuits; CMOS technology; Clocks; Design methodology; Logic circuits; Microprocessors; Power measurement; Power system management; Semiconductor device measurement; System-on-a-chip;
Journal_Title :
Solid-State Circuits, IEEE Journal of
