Title :
Topology dependence of floating gate faults in MOS integrated circuits
Author :
Renovell, M. ; Cambon, G.
Author_Institution :
Université des Sciences et Techniques du Languedoc, Laboratoire d´Automatique et de Microélectronique de Montpellier, Laboratoire associé au CNRS (UA 371), Montpellier, France
Abstract :
Models for floating gate faults in MOS integrated circuits are introduced. It is experimentally demonstrated that these models are mask-topology-dependent. The logic state of the gate can be stuck-at, undefined or influenced. In the case of an influenced gate a `pseudo-MOS transistor¿ is defined.
Keywords :
CMOS integrated circuits; failure analysis; integrated circuit testing; masks; CMOS technology; MOS integrated circuits; circuit testing; domino structure; floating gate faults; influenced gate; logic-state; mask topology; pseudoMOS transistor;
Journal_Title :
Electronics Letters
DOI :
10.1049/el:19860106
