A wafer-scale-level system integrated LSI containing eleven 4-Mb DRAMs, six 64-kb SRAMs, and an 18 K-gate array

Author

Sato, Katsuyuki ; Kobayashi, Mitsuteru ; Hida, Hiroyuki ; Miyazawa, Hideyuki ; Shirai, Yuji ; Fujita, Kenji ; Nakao, Toshiyuki ; Ishihara, Masamichi

Author_Institution

Hitachi Ltd., Tokyo, Japan

Volume

27

Issue

11

fYear

1992

fDate

11/1/1992 12:00:00 AM

Firstpage

1608

Lastpage

1613

Abstract

A system integrated LSI chip (SLSI) that contains eleven 4-Mb DRAMs, six 64-kb SRAMs, and an 18 K-gate array, for a graphics application system is described. To implement the SLSI on a silicon chip, three key techniques have been developed: (1) system redundancy for defect relief; (2) chip configuration and fabrication with blade masking to achieve a hybrid 38.16×50.4-mm² chip; and (3) large-capability and high-reliability 324-pin 54×86-mm² plastic pin grid array package. Using a system redundancy technique, a 60% yield for the SLSI is achieved with a 40% yield for the DRAM itself. That is twice the 30% yield of the conventional repair scheme. Access times are 65 ns for the DRAM and 14 ns for the SRAM with a 3.9-W chip power dissipation

Keywords

CMOS integrated circuits; DRAM chips; SRAM chips; large scale integration; logic arrays; redundancy; 14 ns; 3.9 W; 4 Mbit; 64 kbit; 65 ns; blade masking; chip power dissipation; defect relief; gate array; graphics application system; pin grid array package; plastic PGA package; system integrated LSI chip; system redundancy; wafer-scale-level system; Cache memory; Control systems; Fabrication; Graphics; Large scale integration; Logic arrays; Nonvolatile memory; Packaging; Random access memory; Redundancy;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.165342

Filename

165342