MOSFETs RF Noise Optimization via Channel Engineering

In this letter, we propose a design methodology to enhance the High Frequency noise performance of the traditional CMOS technology via channel engineering. We show that the intrinsic noise correlation coefficient (C) of the conventional CMOS (~0.4 or lower) limits the noise performance. By lateral nonuniformly doping the channel, this value of C can be enhanced to as high as ~0.9 in the weak inversion regime and this in turn improves the NF_min of the device. Key noise parameters are carefully compared and analyzed in detail with the state-of-the-art GaAs-based pHEMT and nanoscaled CMOS technology. This letter offers another viable option for achieving CMOS with low power, low voltage, and with much improved noise performance without the need to scale the device.