A high-performance CMOS redundant binary multiplication-and-accumulation (MAC) unit

Author

Huang, Xiaoping ; Liu, Wen-Jung ; Wei, Belle W Y

Author_Institution

Dept. of Electr. Eng., San Jose State Univ., CA, USA

Volume

41

Issue

1

fYear

1994

fDate

1/1/1994 12:00:00 AM

Firstpage

33

Lastpage

39

Abstract

This paper describes the design of a pipelined CMOS 16×16 redundant binary multiplication-and-accumulation (MAC) unit. The MAC unit uses a novel coding scheme for representing binary signed digits. The coding, integrated with the modified Booth algorithm, produces a factor of four reduction in the number of summands feeding the adder tree without preprocessing. The consequent chip layout is compact and small. Furthermore, the MAC´s pipeline stages are balanced, resulting in a clock rate exceeding 200 MHz with 0.8-μm two-level metal CMOS technology

Keywords

CMOS integrated circuits; adders; digital arithmetic; multiplying circuits; pipeline processing; 0.8 micron; 16 bit; MAC unit; adder tree; binary signed digits; chip layout; clock rate; coding scheme; modified Booth algorithm; pipeline processing; redundant binary multiplication-and-accumulation unit; summands; two-level metal CMOS technology; Adders; BiCMOS integrated circuits; CMOS technology; Clocks; Decoding; Delay; Hardware; Heart; Pipelines; Routing;

fLanguage

English

Journal_Title

Circuits and Systems I: Fundamental Theory and Applications, IEEE Transactions on

Publisher

ieee

ISSN

1057-7122

Type

jour

DOI

10.1109/81.260217

Filename

260217