DocumentCode :
1020421
Title :
Efficient circuit configurations for algorithmic analog to digital converters
Author :
Nagaraj, Krishnaswami
Author_Institution :
AT&T Bell Labs., Allentown, PA, USA
Volume :
40
Issue :
12
fYear :
1993
fDate :
12/1/1993 12:00:00 AM
Firstpage :
777
Lastpage :
785
Abstract :
The authors focus on efficient circuit configurations for algorithmic analog-to-digital (A/D) conversion. Several new circuit configurations which achieve the maximum throughput obtainable from a recirculating architecture while minimizing chip area and power are presented. Results for a 10-b prototype are presented
Keywords :
analogue-digital conversion; linear integrated circuits; monolithic integrated circuits; 10-b prototype; algorithmic analog to digital converters; chip area; chip power; circuit configurations; linear ICs; recirculating architecture; throughput; Analog-digital conversion; Artificial intelligence; Capacitors; Circuits; Digital arithmetic; Latches; Operational amplifiers; Prototypes; Throughput; Voltage;
fLanguage :
English
Journal_Title :
Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on
Publisher :
ieee
ISSN :
1057-7130
Type :
jour
DOI :
10.1109/82.260242
Filename :
260242
Link To Document :
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