Title :
Piezoelectric microphone with on-chip CMOS circuits
Author :
Ried, Robert P. ; Kim, Eun Sok ; Hong, David M. ; Muller, Richard S.
Author_Institution :
Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
fDate :
9/1/1993 12:00:00 AM
Abstract :
An IC-processed piezoelectric microphone with on-chip, large-scale integrated (LSI) CMOS circuits has been designed, fabricated, and tested in a joint, interactive process between a commercial CMOS foundry and a university micromachining facility. The 2500×2500×3.5 μm 3 microphone has a piezoelectric ZnO layer on a supporting low-pressure chemical-vapor-deposited (LPCVD), silicon-rich, silicon nitride layer. The optimum residual-stress-compensation scheme for maximizing microphone sensitivity produces a slightly buckled microphone diaphragm. A model for the sensitivity dependence of device operation to residual stress is confirmed by applying external strain. The packaged microphone has a resonant frequency of 18 kHz, a quality factor Q≈40, and an unamplified sensitivity of 0.92 mV/Pa. Differential amplifiers provide 49 dB gain with 13 μV A-weighted noise at the input
Keywords :
CMOS integrated circuits; CVD coatings; compensation; integrated circuit technology; internal stresses; large scale integration; microphones; piezoelectric transducers; silicon compounds; substrates; zinc compounds; 13 muV; 18 kHz; 49 dB; LSI; Si3N4; ZnO-Si3N4; acoustic model; buckled microphone diaphragm; differential amplifiers; external strain; fabrication; interactive process; low-pressure chemical-vapor-deposition; micromachining facility; microphone sensitivity; on-chip CMOS circuits; optimum residual-stress-compensation; packaged microphone; piezoelectric ZnO layer; piezoelectric microphone; quality factor; residual stress; resonant frequency; CMOS process; Chemicals; Circuit testing; Foundries; Large scale integration; Micromachining; Microphones; Semiconductor device modeling; Silicon; Zinc oxide;
Journal_Title :
Microelectromechanical Systems, Journal of
