Title :
DPTL 4-b carry lookahead adder
Author :
Mittal, Manish ; Salama, C. Andre T
Author_Institution :
Dept. of Electr. Eng., Toronto Univ., Ont., Canada
fDate :
11/1/1992 12:00:00 AM
Abstract :
Implementation of a 4-b carry lookahead adder using D-MESFETs, in 1-μm non-self-aligned gate GaAs technology, is presented. A novel technique to improve the circuit performance using differential pass transistor logic (DPTL) is presented. Circuit structures are presented and are compared with buffered FET logic (BFL). Experimental results are provided to verify the functionality and performance of the DPTL adder. The adder occupies an area of 0.890×0.652 mm2 (excluding the output pads) and can add up to 1 Gwords/s dissipating 242 mW of power (excluding the output drivers)
Keywords :
III-V semiconductors; Schottky gate field effect transistors; adders; digital arithmetic; field effect integrated circuits; gallium arsenide; integrated logic circuits; 1 micron; 242 mW; D-MESFETs; GaAs technology; carry lookahead adder; differential pass transistor logic; Adders; Boolean functions; Degradation; Equations; Gallium arsenide; Logic circuits; Logic design; Logic gates; Propagation delay; Signal design;
Journal_Title :
Solid-State Circuits, IEEE Journal of
