DocumentCode
1020900
Title
Multiway partitioning via geometric embeddings, orderings, and dynamic programming
Author
Alpert, Charles J. ; Kahng, Andrew B.
Author_Institution
Dept. of Comput. Sci., California Univ., Los Angeles, CA, USA
Volume
14
Issue
11
fYear
1995
fDate
11/1/1995 12:00:00 AM
Firstpage
1342
Lastpage
1358
Abstract
This paper presents effective algorithms for multiway partitioning. Confirming ideas originally due to Hall (1970), we demonstrate that geometric embeddings of the circuit netlist can lead to high-quality k-way partitionings. The netlist embeddings are derived via the computation of d eigenvectors of the Laplacian for a graph representation of the netlist. As Hall did not specify how to partition such geometric embeddings, we explore various geometric partitioning objectives and algorithms, and find that they are limited because they do not integrate topological information from the netlist. Thus, we also present a new partitioning algorithm that exploits both the geometric embedding and netlist information, as well as a restricted partitioning formulation that requires each cluster of the k-way partitioning to be contiguous in a given linear ordering. We begin with a d-dimensional spectral embedding and construct a heuristic 1-dimensional ordering of the modules (combining spacefilling curve with 3-Opt approaches originally proposed for the traveling salesman problem). We then apply dynamic programming to efficiently compute the optimal k-way split of the ordering for a variety of objective functions, including Scaled Cost and Absorption. This approach can transparently integrate user-specified cluster size bounds. Experiments show that this technique yields multiway partitionings with lower Sealed Cost than previous spectral approaches
Keywords
VLSI; circuit optimisation; dynamic programming; eigenvalues and eigenfunctions; graph theory; logic CAD; logic partitioning; network topology; VLSI; circuit netlist; circuit optimisation; dynamic programming; eigenvectors; geometric embeddings; graph representation; heuristic 1-dimensional ordering; k-way partitionings; linear ordering; logic partitioning; multiway partitioning; objective functions; optimal k-way split; restricted partitioning formulation; spacefilling curve; spectral embedding; topological information; user-specified cluster size bounds; Associate members; Circuits; Clustering algorithms; Design methodology; Dynamic programming; Embedded computing; Hardware design languages; Partitioning algorithms; Signal synthesis; Software design;
fLanguage
English
Journal_Title
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
Publisher
ieee
ISSN
0278-0070
Type
jour
DOI
10.1109/43.469661
Filename
469661
Link To Document