Low-Power SRAMs in Nanoscale CMOS Technologies

Author

Zhang, Kevin ; Hamzaoglu, Fatih ; Wang, Yih

Author_Institution

Intel Corp., Hillsboro

Volume

55

Issue

1

fYear

2008

Firstpage

145

Lastpage

151

Abstract

As CMOS technology scaling is advancing beyond 100 nm, it has become increasingly difficult to meet the power and performance goals for various product applications while achieving aggressive area scaling in static random access memory (SRAM) development. This paper addresses many of the most pressing challenges in today´s SRAM design from perspectives of both process technology optimization and design innovation. Key process tradeoff and optimization along with the advanced circuit design techniques for power management and low-voltage operation are discussed.

Keywords

CMOS memory circuits; SRAM chips; circuit optimisation; integrated circuit design; low-power electronics; CMOS technology scaling; advanced circuit design; design innovation; low-power SRAM; nanoscale CMOS technologies; power management; process technology optimization; process tradeoff; static random access memory; CMOS technology; Circuit synthesis; Design optimization; Energy consumption; Integrated circuit technology; Logic circuits; Paper technology; Random access memory; SRAM chips; Very large scale integration; Cache; low-power circuits; static random access memory (SRAM);

fLanguage

English

Journal_Title

Electron Devices, IEEE Transactions on

Publisher

ieee

ISSN

0018-9383

Type

jour

DOI

10.1109/TED.2007.911356

Filename

4408817