Title :
Shrinking wide compressors [BIST]
Author_Institution :
PowerPC Dev. Centre, IBM Syst. Technol. & Archit., Austin, TX, USA
fDate :
11/1/1995 12:00:00 AM
Abstract :
Quite often built-in self-test (BIST) designs make use of multiple-input signature registers (MISR´s) to compress the test data. Normally a MISR includes a stage for every signal that it is sampling. In some applications this leads to very wide MISR´s that may include several hundred stages. Wide MISR´s pose problems in terms of hardware and wiring overhead. Shorter compressors are, therefore, needed. This paper investigates the problem of shrinking an MISR so that it samples multiple signals at every stage. The ultimate shrinkage occurs when only the parity of the sampled signals is compressed. This is the case when a MISR is replaced by a single-input signature register (SISR). Issues like detection probability loss, test length penalty, and fault coverage degradation are some of the disadvantages that may arise from the MISR shrinkage. Minimizing the effect of these issues is a precondition to the success of this method
Keywords :
built-in self test; data compression; integrated circuit testing; logic design; logic testing; probability; BIST designs; MISR shrinkage; built-in self-test; detection probability loss; fault coverage degradation; multiple-input signature registers; test data compression; test length penalty; Automatic testing; Built-in self-test; Circuit faults; Circuit testing; Compressors; Degradation; Fault detection; Hardware; Jacobian matrices; Packaging;
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on