Use of sacrificial spacers for fabricating LDD transistors in a CMOS process

The use of sacrificial spacers for LDD transistors in a CMOS process is described. LPCVD nitride or PSG is employed as the sidewall-spacer material which is selectively etched off after the LDD´s n-/n+ junction formation, thus allowing subsequent shallow p+ implant self-aligning to the polysilicon gate. Deeper n-/n+ junctions with adequate drain/gate overlap for n-channel LDD transistors to minimise hot-electron effects can then be made while simultaneously the shallow p+ junction with high punch-through immunity is preserved for p-channel transistors. The conflicting diffusion requirements in forming n-/n+ and p+ source-drain junction depths are therefore decoupled.