• DocumentCode
    1022571
  • Title

    High-speed and high-coding-gain Viterbi decoder with low power consumption employing SST (scarce state transition) scheme

  • Author

    Kubota, Sho ; Ohtani, Kiyonobu ; Kato, Shigeo

  • Author_Institution
    NTT Radio Communication Networks Laboratories, Satellite Communication Department, Satellite Communications Systems Section, Yokosuka, Japan
  • Volume
    22
  • Issue
    9
  • fYear
    1986
  • Firstpage
    491
  • Lastpage
    493
  • Abstract
    A high-speed and high-coding-gain Viterbi decoder LSI with low power consumption is developed using CMOS master-slice LSI. By employment of the SST (scarce state transition) scheme, this LSI achieves a good Pe performance (4.2 dB net coding gain at Pe = 1 × 10-6), drastic reduction of power consumption and number of gates with low development costs.
  • Keywords
    CMOS integrated circuits; decoding; digital integrated circuits; large scale integration; CMOS masterslice LSI; Viterbi decoder; digital IC; forward error correction; high-coding-gain; high-speed; low power consumption; scarce state transition;
  • fLanguage
    English
  • Journal_Title
    Electronics Letters
  • Publisher
    iet
  • ISSN
    0013-5194
  • Type

    jour

  • DOI
    10.1049/el:19860334
  • Filename
    4256528
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1022571