DocumentCode :
1022679
Title :
An efficient architecture for fault-tolerant ATM switches
Author :
Padmanabhan, Krishnan
Author_Institution :
AT&T Bell Labs., Murray Hill, NJ, USA
Volume :
3
Issue :
5
fYear :
1995
fDate :
10/1/1995 12:00:00 AM
Firstpage :
527
Lastpage :
537
Abstract :
A cost-effective fault-tolerant architecture called FAUST is presented for ATM switches. The key idea behind the architecture is the incorporation of spare units and associated commutation logic into strategic partitions of the switching system. The definition of a replaceable unit is flexible, and based on packaging considerations. The commutation logic can switch in a spare unit in place of a failed one at cell rate, and is distributed entirely in the existing switch control units. So the additional overhead is almost entirely in the spare modules provided. The technique is far superior to a duplex configuration in terms of reliability improvement vs. component redundancy, and can be applied to established architectures for ATM switches, including multistage sort and shared memory based architectures. Its scalability also makes it applicable to system sizes from a few tens of lines to a few thousand
Keywords :
asynchronous transfer mode; shared memory systems; telecommunication network reliability; FAUST; commutation logic; component redundancy; efficient architecture; fault-tolerant ATM switches; multistage sort and shared memory based architectures; packaging; reliability improvement; replaceable unit; scalability; spare modules; spare units; strategic partitions; switch control units; switching system; Asynchronous transfer mode; Costs; Fault tolerance; Fault tolerant systems; Hardware; Logic; Memory architecture; Prototypes; Switches; Switching systems;
fLanguage :
English
Journal_Title :
Networking, IEEE/ACM Transactions on
Publisher :
ieee
ISSN :
1063-6692
Type :
jour
DOI :
10.1109/90.469953
Filename :
469953
Link To Document :
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