DocumentCode
1023334
Title
Backside thinned CMOS imagers with high broadband quantum efficiency realised using new integration process
Author
Munck, K. De ; Bogaerts, J. ; Tezcan, D.S. ; Moor, P. De ; Sedky, S. ; Hoof, C. Van
Author_Institution
KU Leuven, Leuven
Volume
44
Issue
1
fYear
2008
Firstpage
50
Lastpage
52
Abstract
Thinned backside illuminated CMOS imagers were developed, having a thick epitaxial layer with a graded doping concentration. All thin wafer processing is performed on 200 mm wafers using a specially developed temporary carrier process. Following appropriate backside treatment, high quantum efficiency above 80% between 400 and 870 nm was obtained, in agreement with simulation.
Keywords
CMOS image sensors; semiconductor epitaxial layers; wafer-scale integration; backside thinned CMOS imagers; broadband quantum efficiency; integration process; size 200 mm; thick epitaxial layer; thin wafer processing;
fLanguage
English
Journal_Title
Electronics Letters
Publisher
iet
ISSN
0013-5194
Type
jour
DOI
10.1049/el:20082812
Filename
4415025
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