High-speed measurements of single gates; Higher-voltage gates

The gate delay of a single CIL AND gate is measured with a Josephson sampler. The CIL gate consists of a CIL interferometer preceded by a three-junction SQUID isolation stage. The smallest delay observed was 6 ps. Simulation results and sampling measurements of a gate designed to switch to 3Vgare also reported. Processing variations precluded successful operation of the higher-voltage gate. The simulations suggest that this failure is due to the large difference of the average critical current from the design value. Scaling arguments show that for small-scale circuits high-speed operation with gate delays of a few picoseconds can be achieved with junction dimensions approximately equal to the Josephson penetration depth.