Flooding-based watershed algorithm and its prototype hardware architecture

Watershed transformation is a powerful image segmentation technique. The potential of its real-time application can be realised by a dedicated hardware architecture. However, little work has been reported so far on hardware realisation of watershed transformation. The authors propose an improved watershed algorithm derived from Meyer´s simulated flooding-based algorithm by ordered queues and a prototype FPGA-based architecture for its effective implementation. The improvement in computational complexity results from use of a single queue and conditional neighbourhood comparisons while processing the 3 × 3 neighbouring pixels. Besides analysing the computational complexity of the principal steps of the proposed algorithm, the authors present simulation results of running the proposed algorithm and the conventional algorithm on different images for comparison. The proposed architecture has been modelled in VHDL and synthesised for Virtex FPGA. The implementation results show acceptable performance of the proposed architecture.