• DocumentCode
    1024505
  • Title

    Envelope signal selective emphasis in a polar radio frequency transmitter architecture

  • Author

    Martires, J. ; Christensen, S.B. ; Larsen, Torben

  • Volume
    2
  • Issue
    6
  • fYear
    2008
  • fDate
    12/1/2008 12:00:00 AM
  • Firstpage
    509
  • Lastpage
    517
  • Abstract
    The linearity of an efficient polar transmitter architecture, with a 1 bit oversampled delta sigma (DeltaSigma) modulating the envelope signal, depends, to a high degree, on low-pass envelope filtering. This filter is compulsory to attenuate the DeltaSigma quantisation noise. A high cut-off frequency results in more noise being included. In contrast, using a filter with a low cut-off frequency results in attenuation of the information content of the envelope signal. Either way, the result is unwanted spectral regrowth. By pre-emphasising the envelope signal, the filter s attenuation of the information is mitigated. The pre-emphasis is implemented by a digital pseudo-derivative high-pass filter, with inverse magnitude characteristics of the analogue low-pass filter, within a limited interest band. Consequently, the low-pass filter can be designed with a lower cut-off frequency to attenuate more of the DeltaSigma modulator noise, and the modulator can switch at lower frequencies. With this technique, the WLAN output spectrum, at the critical 30 MHz offset corner frequency, is improved by 12.5 dB, considering a second order DeltaSigma sampling at 1.28 GHz. The technique was verified with an experimental setup and the behaviour agrees well with simulations.
  • Keywords
    delta-sigma modulation; digital filters; high-pass filters; low-pass filters; radio transmitters; wireless LAN; DeltaSigma modulator noise; DeltaSigma quantisation noise; WLAN output spectrum; analogue low-pass filter; digital pseudo-derivative high-pass filter; envelope signal selective emphasis; frequency 1.28 GHz; low-pass envelope filtering; oversampled delta-sigma modulation; polar radio frequency transmitter architecture;
  • fLanguage
    English
  • Journal_Title
    Circuits, Devices & Systems, IET
  • Publisher
    iet
  • ISSN
    1751-858X
  • Type

    jour

  • DOI
    10.1049/iet-cds:20080057
  • Filename
    4703175