Synergistic fault-tolerance for memory chips

Author

Stapper, Charles H. ; Lee, Hsing-San

Author_Institution

IBM, Essex Junction, VT, USA

Volume

41

Issue

9

fYear

1992

fDate

9/1/1992 12:00:00 AM

Firstpage

1078

Lastpage

1087

Abstract

The discovery of a principle of synergistic fault tolerance is described, and it is shown analytically why it occurs. The performance of its hardware implementation, in the form of a VLSI memory chip, is reported. An analysis of the error-correction scheme implemented in the hardware is presented, and limitations to the use of error-correcting codes for fault tolerance are explained. Methods for circumventing these limitations with the use of redundant circuits are discussed, analyzing the effect of bitline and wordline redundancy. The result of the analysis shows how the combination of error-correcting codes with redundant circuitry results in a fault-tolerance synergism

Keywords

DRAM chips; VLSI; error correction codes; fault tolerant computing; VLSI memory chip; bitline redundancy; error-correcting codes; error-correction; fault-tolerance synergism; memory chips; redundant circuits; synergistic fault tolerance; wordline redundancy; Circuit faults; Error correction codes; Fabrication; Fault tolerance; Hardware; Integrated circuit yield; Manufacturing; Mathematical analysis; Protection; Very large scale integration;

fLanguage

English

Journal_Title

Computers, IEEE Transactions on

Publisher

ieee

ISSN

0018-9340

Type

jour

DOI

10.1109/12.165390

Filename

165390