A 10-b 20-MHz 30-mW pipelined interpolating CMOS ADC

Author

Kusumoto, Keiichi ; Matsuzawa, Akira ; Murata, Kenji

Author_Institution

Semicond. Res. Center, Matsushita Electr. Ind. Co. Ltd., Osaka, Japan

Volume

28

Issue

12

fYear

1993

fDate

12/1/1993 12:00:00 AM

Firstpage

1200

Lastpage

1206

Abstract

This paper describes a circuit design and experimental results of a video-rate 10-b analog-to-digital converter (ADC) suitable for portable audio-visual equipment. Two new circuit techniques, termed pipelined capacitive interpolation and error averaging circuits with capacitor networks, are developed. As a result, very low power dissipation of 30 mW at a low power-supply voltage of 2.5 V is attained at the conversion frequency of 20 MHz. Also, a good DNL of less than ±0.5 LSB and an acceptable signal-to-noise and distortion ratio of 55 dB are obtained for the input frequencies of 1 kHz and 1 MHz, respectively. The ADC is fabricated in 0.8-μm CMOS technology and occupies an area of 2.6×2.5 mm²

Keywords

CMOS integrated circuits; analogue-digital conversion; audio-visual systems; interpolation; pipeline processing; video signals; 0.8 mum; 1 kHz to 1 MHz; 2.5 V; 20 MHz; 30 mW; CMOS technology; DNL; capacitor networks; circuit design; conversion frequency; distortion ratio; error averaging circuits; low power dissipation; low power-supply voltage; pipelined capacitive interpolation; pipelined interpolating CMOS ADC; portable audio-visual equipment; signal-to-noise ratio; video-rate analog-to-digital converter; CMOS analog integrated circuits; CMOS technology; Capacitors; Circuit synthesis; Energy consumption; Interpolation; Low voltage; Operational amplifiers; Power supplies; Preamplifiers;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.261992

Filename

261992