A 15-b 1-Msample/s digitally self-calibrated pipeline ADC

Author

Karanicolas, Andrew N. ; Lee, Hae-Seung ; Barcrania, K.L.

Author_Institution

Dept. of Electr. Eng., Massachusetts Inst. of Technol., Cambridge, MA, USA

Volume

28

Issue

12

fYear

1993

fDate

12/1/1993 12:00:00 AM

Firstpage

1207

Lastpage

1215

Abstract

A 15-b 1-Msample/s digitally self-calibrated pipeline analog-to-digital converter (ADC) is presented. A radix 1.93, 1 b per stage design is employed. The digital self-calibration accounts for capacitor mismatch, comparator offset, charge injection, finite op-amp gain, and capacitor nonlinearity contributing to DNL. A THD of -90 dB was measured with a 9.8756-kHz sine-wave input. The DNL was measured to be within ±0.25 LSB at 15 b, and the INL was measured to be within ±1.25 LSB at 15 b. The die area is 9.3 mm×8.3 mm and operates on ±4-V power supply with 1.8-W power dissipation. The ADC is fabricated in an 11-V, 4-GHz, 2.4-μm BiCMOS process

Keywords

BiCMOS integrated circuits; analogue-digital conversion; calibration; pipeline processing; switched capacitor networks; 1.8 W; 11 V; 2.4 mum; 4 GHz; 4 V; 9.8756 kHz; BiCMOS process; DNL; INL; THD; analog-to-digital converter; die area; digital self-calibration; digitally self-calibrated pipeline ADC; power dissipation; radix 1.93 1 b per stage design; Analog-digital conversion; Approximation algorithms; BiCMOS integrated circuits; Calibration; Capacitors; Clocks; Operational amplifiers; Pipelines; Power dissipation; Power supplies;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.261994

Filename

261994