Title :
A 300-MHz 16-b BiCMOS video signal processor
Author :
Inoue, Toshiaki ; Goto, Junichi ; Yamashina, Masakazu ; Suzuki, Kazumasa ; Nomura, Masahiro ; Koseki, Youichi ; Kimura, Tohru ; Atsumo, Takao ; Motomura, Masato ; Shih, Benjamin S. ; Horinchi, T. ; Hamatake, Nobuhisa ; Kumagai, Kouichi ; Enomoto, Tadayosh
Author_Institution :
Microelectron. Res. Labs., NEC Corp., Sagamihara, Japan
fDate :
12/1/1993 12:00:00 AM
Abstract :
A 300-MHz 16-b full-programmable parallel-pipelined video signal processor ULSI has been developed. With multifunctional arithmetic units to achieve parallel vector processing, and with a phase-locked-loop (PLL) type clock generator to help attain the 300-MHz internal operating speed, this ULSI is able to attain, with only one chip, 30-frame-per-second full-CIF video data coding based on CCITT H.261. Two different types of pass-transistor BinMOS circuits have been developed to help achieve an access time of 3 ns for a 146-kb SRAM and for data buses. Fabricated with a 0.5-μm BiCMOS and triple-layer metallization process technology, the video signal processor ULSI contains 1.27-million transistors in a 16.5×17.0-mm2 die area
Keywords :
BiCMOS integrated circuits; VLSI; digital arithmetic; digital signal processing chips; image coding; pipeline processing; video signals; 0.5 micron; 16 bit; 30-frame-per-second full-CIF video data coding; 300 MHz; BiCMOS video signal processor; CCITT H.261; SRAM; ULSI; access time; clock generator; data buses; full-programmable parallel-pipelined processor; internal operating speed; multifunctional arithmetic units; pass-transistor BinMOS circuits; phase-locked-loop; triple-layer metallization process; Arithmetic; BiCMOS integrated circuits; Clocks; Data buses; Frequency; Metallization; Phase locked loops; Random access memory; Signal processing; Ultra large scale integration;
Journal_Title :
Solid-State Circuits, IEEE Journal of
