Title :
A 5.8-ns 256-Kb BiCMOS TTL SRAM with T-Shaped bit line architecture
Author :
Shiomi, Toru ; Wada, Tomohisa ; Ohbayashi, Shigeki ; Ohba, Atsushi ; Honda, Hiroki ; Ishigaki, Yoshiyuki ; Hine, Shiro ; Anami, Kenji ; Suzuki, Kimio ; Sumi, Tadashi
Author_Institution :
Mitsubishi Electr. Corp., Itami, Japan
fDate :
12/1/1993 12:00:00 AM
Abstract :
Presents a new bit line architecture named T-shaped bit line architecture (TSBA), which is suitable for high speed, high density, and/or large bit-wide configuration SRAMs. TSBA, utilizing orthogonal complimentary bit lines in parallel with the word lines, is the solution to bit line pitch constraint for direct bipolar column sensing. This TSBA is applied to a 256-Kb SRAM with a typical access time of 5.8 ns. To achieve access times below 6 ns, this SRAM employs a bipolar Darlington column sense amplifier, a hierarchical column decoding scheme, a data bus shielding layout combined with TSBA, and a 0.8-μm BiCMOS technology
Keywords :
BiCMOS integrated circuits; SRAM chips; memory architecture; 0.8 micron; 0.8-μm BiCMOS technology; 256 Kbit; 5.8 ns; BiCMOS TTL SRAM; T-Shaped bit line architecture; access time; bipolar Darlington column sense amplifier; bit line pitch constraint; data bus shielding layout; direct bipolar column sensing; hierarchical column decoding scheme; orthogonal complimentary bit lines; Architecture; BiCMOS integrated circuits; Bipolar transistors; Cache memory; Decoding; Fabrication; Microprocessors; Packaging; Random access memory; Switches;
Journal_Title :
Solid-State Circuits, IEEE Journal of
