Suitable polynomials for aliasing reduction by test vector reversal in signature analysers

Reversing test vector order has been recommended by some authors as a scheme to reduce aliasing in signature analysis of single-output logic circuits using linear feedback shift registers. The letter analyses the method from the approach of determining if it is valid for all characteristic polynomaials. It is concluded that there is a range of polynomials for which reversal of test vector order has no effect on aliasing reduction.