High-speed low-power Darlington ECL circuit

Author

Chuang, C.T. ; Chin, K. ; Lu, P.F. ; Shin, H.J.

Author_Institution

IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA

Volume

28

Issue

12

fYear

1993

fDate

12/1/1993 12:00:00 AM

Firstpage

1374

Lastpage

1376

Abstract

Presents an ECL circuit with a Darlington configured dynamic current source and active-pull-down emitter-follower stage for low-power high-speed gate array application. The dynamic current source provides a large dynamic current during the switching transient to improve the power delay of the logic stage (current switch). A novel self-biasing scheme for the dynamic current source and the active-pull-down transistor with no additional devices and power in the biasing circuit is described. Based on a 0.8-μm double-poly self-aligned bipolar technology at a power consumption of 1 mW/gate, the circuit offers 28% improvement in the loaded (FI/FO=3, C_L=0.3 pF) delay and 42% improvement in the load driving capability compared with the conventional ECL circuit. The design and scaling considerations of the circuit are discussed

Keywords

bipolar integrated circuits; emitter-coupled logic; integrated circuit technology; logic arrays; 0.8 micron; Darlington ECL circuit; active-pull-down emitter-follower stage; double-poly self-aligned bipolar technology; dynamic current source; load driving capability; low-power high-speed gate array application; power consumption; power delay; scaling considerations; self-biasing scheme; switching transient; Delay; Energy consumption; Helium; Logic devices; Resistors; Solid state circuits; Steady-state; Switches; Switching circuits; Voltage;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.262014

Filename

262014