DocumentCode :
1026172
Title :
A systolic power-sum circuit for GF(2m)
Author :
Wei, Shyue-Win
Author_Institution :
China Coll. of Eng., Hsin-Chu, Taiwan
Volume :
43
Issue :
2
fYear :
1994
fDate :
2/1/1994 12:00:00 AM
Firstpage :
226
Lastpage :
229
Abstract :
A systolic power-sum circuit designed to perform AB2+C computations in the finite field GF(2m) is presented, where A, B, and C are arbitrary elements of GF(2m). This new circuit is constructed by m2 identical cells, each of which consists of three 2-input AND logical gates, one 2-input XOR gate, one 3-input XOR gate, and ten latches. The AB2+C computation is required in decoding many error-correcting codes. The paper shows that a decoder implemented using the new power-sum circuit will have less complex circuitry and shorter decoding delay than one implemented using conventional product-sum multipliers
Keywords :
error correction codes; logic circuits; logic gates; systolic arrays; decoding; error-correcting codes; finite field; logical gates; power-sum circuit; systolic power-sum circuit; Arithmetic; Circuits; Computer architecture; Decoding; Delay; Error correction; Error correction codes; Galois fields; Logic gates; Polynomials;
fLanguage :
English
Journal_Title :
Computers, IEEE Transactions on
Publisher :
ieee
ISSN :
0018-9340
Type :
jour
DOI :
10.1109/12.262128
Filename :
262128
Link To Document :
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