Title :
Method to reduce the sign bit extension in a multiplier that uses the modified Booth algorithm
Author_Institution :
Philips International Institute of Technological Studies, Eindhoven, Netherlands
Abstract :
A technique that reduces the number of full adders that are used to implement the modified Booth algorithm is described. This technique is based on the need to extend the sign bit of the partial products and on the redundancy that is implicit in this operation.
Keywords :
digital arithmetic; multiplying circuits; digital arithmetic; full adder array reduction; modified Booth algorithm; multiplier; partial products; redundancy; sign bit extension;
Journal_Title :
Electronics Letters
DOI :
10.1049/el:19860727
