Title :
Design validation: comparing theoretical and empirical results of design error modeling
Author :
Kang, Sungho ; Szygenda, S.A.
Author_Institution :
Motorola Inc., Austin, TX, USA
Abstract :
To use simulation for design verification, designers need a confidence measure for a given set of simulation patterns, specifically for cases in which only a subset of the possible patterns is used. The authors derive a measure of design verification coverage based on the number of design errors detected in a theoretical analysis of a circuit. To verify the theoretical analysis, they simulate errors and compare the results.<>
Keywords :
circuit CAD; circuit analysis computing; digital simulation; formal verification; confidence measure; design error modeling; design errors; design validation; digital system design; empirical results; simulation; simulation patterns; theoretical analysis; Circuit analysis computing; Circuit simulation; Combinational circuits; Computational modeling; Computer errors; Digital systems; Equations; Process design; Testing;
Journal_Title :
Design & Test of Computers, IEEE
