A high-speed shuffle bus for VLSI arrays

A high-speed shuffle bus which is able to implement various kinds of communication schemes for VLSI processor arrays is presented. Because of the simple and modular nature of the shuffle bus, the processor arrays can now be easily modularized and equipped with flexible capabilities for both global and neighboring communications. With data swapping at a rate as high as 200 MHz between adjacent registers, the shuffle bus is about 20 times faster than those bidirectional pipelined buses. The shuffle bus may be expanded to accommodate any number of nodes with an arbitrary number of bits in each word. With only a few sets of control patterns, the shuffle bus can be applied to the implementation of a wide variety of interconnection networks, sorting networks, FIFO, and associative memory.<>