A Low-Power, Highly Scalable, Vertical Double-Gate MOSFET Using Novel Processes

A sub-45-nm body thickness, vertical-channel, double-gate MOSFET (VDFET) is fabricated on a bulk silicon substrate. The process, in principle, is scalable down to sub-5-nm body thicknesses. It is realized that using very coarse lithography (~1 mum resolution) does not require chemical-mechanical polarization (CMP), and is capable of being integrated with a planar CMOS flow. It relies on the following key, novel, unit processes: (1) a spacer process capable of thickness down to 5 nm; (2) an additional self-aligned process for obtaining a thicker bottom/corner oxide, thus, minimizing leakage and parasitic capacitance; (3) a novel drain contact process including etch stop and implant. Each unit process, by itself, exhibits the versatility to be used in other applications too. Various implant conditions, order of implant step, and starting substrate dopings are studied, and best conditions identified through TSUPREM4 simulations, and later, through experiments to ensure process robustness and dopant tunability for the thin-body vertical double-gate MOSFETs (VDFETs). Drain was implanted separately for better channel length control. Excellent electrical properties in terms of I_d - V_ds,Id - V_gs, and I_g - V_gs are measured. Electrical results show excellent short-channel effect (SCE) immunity and close to an ideal subthreshold slope (64 mV/dec), resulting in a very high I_ON-I_OFF ratio. In addition, the impact of body thickness and the drain contact area on I-V curves and the impact of the Si₃N₄ etch-stop layer on channel current enhancement are studied.