Circuit aspects of transistor parametric frequency doublers

Factors determining the performance of a transistor parametric frequency doubler are considered from the transistor equivalent network viewpoint, emphasising the integral nature of the active and parametric regions. On the basis of a simple transistor model connected as a frequency doubler, it is shown that a higher loading of the harmonic circuit is required than for a conventional varactor multiplier. By use of circuit models which incorporate parasitics inherent in a high-power, high-frequency planar transistor structure, it is shown that more efficient pumping of the varactor region is possible than would be predicted from the standard equivalent circuit models.