Fuzzy logic arbiters for multiple-bus multiprocessor systems

This paper describes and evaluates the use of fuzzy logic arbiters for multiple-bus shared memory multiprocessor system. Multiple-bus systems allow multiple and simultaneous bus transfer in addition to a high degree of fault tolerance. In such systems, arbiters are used to resolve conflicts to system resources, which are the shared memory modules and the buses. Typically, these conflicts are resolved by using two-stage arbitration schemes that employ policies such as random choice, daisy chaining, round-robin, etc. A new way of implementing these arbiters is the use of fuzzy logic to resolve resource request conflicts based on the system state and performance variables. This paper describes a new technique for implementation of fuzzy logic in the system arbiters and presents a simulation program that evaluates the system performance. The program is coded in such a way as to accommodate any arbitration scheme, from which the fixed priority and fuzzy priority have been implemented. Parameters affecting multiple-bus system performance are considered and used as inputs to the fuzzy arbiters. The inputs are fuzzified by using appropriate membership functions, and rules have been defined in such a way as to increase and distribute evenly the acceptance probability of each processor in the system. Results from the simulation program using a prioritized arbitration scheme are compared against other published results and show very close agreement. Furthermore, results show an increase in the acceptance probability of the processors using fuzzy arbiters.