An analytical charge-based compact delay model for submicrometer CMOS inverters

Author

Rosselló, José Luis ; Segura, Jaume

Author_Institution

Phys. Dept., Balearic Islands Univ., Palma de Mallorca, Spain

Volume

51

Issue

7

fYear

2004

fDate

7/1/2004 12:00:00 AM

Firstpage

1301

Lastpage

1311

Abstract

We develop an accurate analytical expression for the propagation delay of submicrometer CMOS inverters that takes into account the short-circuit current, the input-output coupling capacitance, and the carrier velocity saturation effects, of increasing importance in submicrometer CMOS technologies. The model is based on the nth-power-law MOSFET model and computes the delay from the charge delivered to the gate. Comparison with HSPICE level 50 simulations and other previously published models for a 0.18-μm and a 0.35-μm process technologies show significant improvements over previous models.

Keywords

CMOS integrated circuits; MOSFET; SPICE; delay estimation; invertors; semiconductor device models; 0.18 micron; 0.35 micron; HSPICE; analytical compact delay model; analytical model; carrier velocity saturation; charge-based compact delay model; circuit modeling; delay estimation; input-output coupling capacitance; propagation delay; short-circuit current; submicrometer CMOS inverters; submicrometer MOSFET; CMOS technology; Capacitance; Circuit simulation; Computational modeling; Delay effects; Delay estimation; Inverters; MOSFET circuits; Propagation delay; Semiconductor device modeling; Analytical model; circuit modeling; delay estimation; submicrometer MOSFETs;

fLanguage

English

Journal_Title

Circuits and Systems I: Regular Papers, IEEE Transactions on

Publisher

ieee

ISSN

1549-8328

Type

jour

DOI

10.1109/TCSI.2004.830692

Filename

1310501