Timing analysis of asynchronous block transfer cycles on VME and VME64x physical layers

Since its introduction in the early 1980s, the VMEbus plays a leading role in the embedded computing, real-time control and data acquisition systems for high energy physics experiments. In more than 20 years, the original standard has undergone major improvements and new features have been added to physical and logical layers, yet retaining a backward compatibility to protect investments and products life. High-speed data transactions are one of the most important features of the protocol in many applications. In this paper, we focus on the performances of the multiplexed block transfer cycle, a 64-bit data burst transaction fully supported by well-established VME64 silicon interfaces and the majority of high-end modules on the market. We confronted VME with VME64x backplane behaviors in light-to-moderate bus loading scenarios. Test results obtained with a blend of VME64 and VME64x-compliant boards are presented and discussed together with the backplanes´ impedance analysis carried out with time domain reflectometry techniques. The impact on the transfer bandwidth of different load topologies is also reviewed.