• DocumentCode
    1029311
  • Title

    Optimizing resource utilization using transformations

  • Author

    Potkonjak, Miodrag ; Rabaey, Jan

  • Author_Institution
    Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
  • Volume
    13
  • Issue
    3
  • fYear
    1994
  • fDate
    3/1/1994 12:00:00 AM
  • Firstpage
    277
  • Lastpage
    292
  • Abstract
    The goal of the high level synthesis process for real time applications is to minimize the implementation cost, while still satisfying all timing constraints. In this paper, the authors present a combination of four conceptually simple, yet powerful, transformations: namely retiming, associativity, commutativity and inverse element law, which can help to further this goal. Since the minimization problem associated with these transformations is NP complete, a new fast iterative improvement probabilistic algorithm has been developed. The effectiveness of the proposed algorithm and the associated transformations is demonstrated in multiple ways: using standard benchmark examples, with the aid of statistical analysis and through a comparison with estimated minimal bounds
  • Keywords
    application specific integrated circuits; iterative methods; logic CAD; minimisation of switching nets; statistical analysis; ASICs; associativity; commutativity; estimated minimal bounds; high level synthesis process; implementation cost; inverse element law; iterative improvement probabilistic algorithm; logic synthesis; real time applications; resource utilization; retiming; statistical analysis; timing constraints; Clocks; Constraint optimization; Cost function; Delay; High level synthesis; IIR filters; Iterative algorithms; Processor scheduling; Resource management; Timing;
  • fLanguage
    English
  • Journal_Title
    Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0278-0070
  • Type

    jour

  • DOI
    10.1109/43.265670
  • Filename
    265670