DocumentCode :
1029371
Title :
Gateways: a technique for adding event-driven behavior to compiled simulations
Author :
Maurer, Peter M. ; Lee, Yun Sik
Author_Institution :
Dept. of Comput. Sci. & Eng., Univ. of South Florida, Tampa, FL, USA
Volume :
13
Issue :
3
fYear :
1994
fDate :
3/1/1994 12:00:00 AM
Firstpage :
338
Lastpage :
352
Abstract :
The gateway technique is a method for switching segments of code into and out of the instruction stream. When added to the straight-line code generated by a compiled simulator, gateways can be used to enhance the performance of the generated code by switching only those segments of code that actually need to be executed into the instruction stream. The convergence algorithm is an oblivious compiled code algorithm that can be used with many different types of circuits, including cyclic asynchronous circuits. In its oblivious form, the convergence algorithm provides only modest gains in performance over interpreted event-driven simulation, but with the addition of gateways, the performance of the algorithm increases significantly. Experimental data shows that with gateways, the convergence algorithm runs in about 1/5th the time required for an interpreted event-driven simulation. Additional work has been done to reduce the amount of code generated by the convergence algorithm, and to enhance the locality of the code to improve its performance on machines with caches. When used with a multi-delay algorithm, gateways allow simulations to be performed in 1/3 the time required by interpreted simulations. Gateways also allow zero-delay simulations to be more responsive to the activity rate of the circuit, and allow event driven simulations to outperform levelized compiled code when the activity rate of the circuit falls below 13%
Keywords :
asynchronous sequential logic; discrete event simulation; logic CAD; logic gates; logic testing; sequential circuits; activity rate; code locality; compiled simulations; convergence algorithm; cyclic asynchronous circuits; event-driven behavior; gateway technique; instruction stream; levelized compiled code; logic simulation; multi-delay algorithm; zero-delay simulations; Asynchronous circuits; Circuit simulation; Computational modeling; Computer simulation; Convergence; Delay; Discrete event simulation; Performance gain; Processor scheduling; Testing;
fLanguage :
English
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
Publisher :
ieee
ISSN :
0278-0070
Type :
jour
DOI :
10.1109/43.265675
Filename :
265675
Link To Document :
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