DocumentCode :
1029408
Title :
A complement-based fast algorithm to generate universal test sets for multi-output functions
Author :
Chen, Beyin ; Lee, Chung Len
Author_Institution :
Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan
Volume :
13
Issue :
3
fYear :
1994
fDate :
3/1/1994 12:00:00 AM
Firstpage :
370
Lastpage :
377
Abstract :
A fast universal test set (UTS) generation algorithm for multi-output functions is presented. The algorithm first generates the UTS for single-output functions by directly Shannon-expanding and complementing the function. This significantly reduces the time complexity and the usage of temporary memory. Also, it stores tests in test cubes to save the size of memory for test storing. Two-six orders of magnitude in computation efficiency improvement and 1-1800 fold for memory saving over the conventional method are achieved. It then merges the generated test cubes for each single-output function into a set of mutually disjoint test cubes to be the UTS for a multi-output function by employing a new compaction technique. The size of UTS thus obtained is 1-20 times smaller than that of UTS without compaction
Keywords :
automatic testing; combinatorial circuits; computational complexity; logic testing; Shannon-expanding; combinational circuits; compaction technique; complement-based fast algorithm; logic testing; multi-output functions; mutually disjoint test cubes; single-output function; time complexity; universal test sets; Circuit faults; Circuit testing; Combinational circuits; Compaction; Councils; Electrical fault detection; Fault detection; Input variables; Logic functions;
fLanguage :
English
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
Publisher :
ieee
ISSN :
0278-0070
Type :
jour
DOI :
10.1109/43.265678
Filename :
265678
Link To Document :
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