Title :
Design of pe structure of a parallel image processor
Author_Institution :
Polish Academy of Sciences, Institute of Computer Science, PKiN, Warsaw, Poland
Abstract :
Efficient cellular logic operator implementation for real-time binary image analysis is discussed and a design for the PE structure of a table-driven parallel processor is described.
Keywords :
computerised picture processing; parallel processing; real-time systems; cellular logic operator implementation; parallel image processor; real-time binary image analysis; table-driven parallel processor;
Journal_Title :
Electronics Letters
DOI :
10.1049/el:19870086
