DocumentCode
1029411
Title
Design of pe structure of a parallel image processor
Author
Owczarczyk, J.
Author_Institution
Polish Academy of Sciences, Institute of Computer Science, PKiN, Warsaw, Poland
Volume
23
Issue
3
fYear
1987
Firstpage
121
Lastpage
122
Abstract
Efficient cellular logic operator implementation for real-time binary image analysis is discussed and a design for the PE structure of a table-driven parallel processor is described.
Keywords
computerised picture processing; parallel processing; real-time systems; cellular logic operator implementation; parallel image processor; real-time binary image analysis; table-driven parallel processor;
fLanguage
English
Journal_Title
Electronics Letters
Publisher
iet
ISSN
0013-5194
Type
jour
DOI
10.1049/el:19870086
Filename
4257361
Link To Document