Title :
3.0 ps switching operation in all-Nb Josephson logic gates
Author :
Kuroda, K. ; Nakano, J. ; Yuda, M. ; Ueki, M.
Author_Institution :
NTT Electrical Communications Laboratories, Atsugi, Japan
Abstract :
A high-speed logic delay of 3.0 ps/gate in a resistor-coupled Josephson logic (RCL) gate chain is attained using a new Nb Josephson integrated circuit technology. Lift-off, Nb stress control and planarisation techniques are used for fabricating high-quality Nb/AlOx/Nb trilayer junctions and reliable Nb wiring. Pd, which is stable during etching, is used as a resistor material.
Keywords :
logic gates; niobium; superconducting logic circuits; 3 ps; Josephson integrated circuit technology; Josephson logic gates; Nb-AlOx-Nb; Pd; high-speed logic delay; liftoff; planarisation techniques; resistor-coupled Josephson logic; stress control; switching operation; trilayer junctions;
Journal_Title :
Electronics Letters
DOI :
10.1049/el:19870116
