DocumentCode :
10300
Title :
Combined MOS–IGBT–SCR Structure for a Compact High-Robustness ESD Power Clamp in Smart Power SOI Technology
Author :
Arbess, Houssam ; Bafleur, Marise ; Tremouilles, David ; Zerarka, Moustafa
Author_Institution :
Lab. d´Anal. et d´Archit. des Syst. (LAAS), Toulouse, France
Volume :
14
Issue :
1
fYear :
2014
fDate :
Mar-14
Firstpage :
432
Lastpage :
440
Abstract :
Smart power technologies are required to withstand high-electrostatic-discharge (ESD) robustness under both powered and unpowered conditions, particularly for automotive and aeronautic applications among many others. They are concurrently confronted to the challenges of high-temperature operation in order to reduce heat-sink-related costs. In this context, very compact high-robustness ESD protections with low sensitivity to temperature are required. To fulfill this need, we studied a new ESD protection structure that combines in the same component MOS, IGBT, and thyristor effects. This is achieved by inserting in the same LDMOS device P+ diffusions in the drain. We studied the impact of N+/P+ ratios on RON and holding current at high temperatures. Structure optimization has been realized with 3-D TCAD simulation and experimentally validated. The proposed structures provide high ESD robustness with small footprint and reduced temperature sensitivity compared with classical solutions. Original design solutions to improve their immunity to latchup are also presented.
Keywords :
CMOS integrated circuits; MIS structures; bipolar integrated circuits; electrostatic discharge; insulated gate bipolar transistors; power integrated circuits; silicon-on-insulator; thyristor applications; MOS-IGBT-SCR structure; aeronautic applications; automotive applications; bipolar CMOS DMOS merged technology; compact high robustness ESD power clamp; high electrostatic discharge robustness; holding current; latchup immunity; smart power SOI technology; structure optimization; thyristor effect; Electrostatic discharges; Insulated gate bipolar transistors; Logic gates; Robustness; Temperature measurement; Temperature sensors; Thyristors; ESD protection; SCR; SOI technology; latch-up; power clamp;
fLanguage :
English
Journal_Title :
Device and Materials Reliability, IEEE Transactions on
Publisher :
ieee
ISSN :
1530-4388
Type :
jour
DOI :
10.1109/TDMR.2013.2281726
Filename :
6600884
Link To Document :
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