Title :
Simplified Hardware Bit Correlator
Author :
Cunat, Christophe ; Boutillon, Emmanuel
Author_Institution :
TurboConcept, Plouzane
fDate :
6/1/2007 12:00:00 AM
Abstract :
This letter proposes a suboptimal implementation of a binary correlator suitable for detecting a known fixed pattern in a binary stream. The theoretical performances in terms of the probability of nondetection and the probability of false alarm are evaluated. These performances show that the degradations are negligible. Compared to a proprietary core provided by FPGA vendor, this implementation allows a 15 % look-up table reduction, a 30 % register reduction and up to a 30 % higher clock frequency in a FPGA.
Keywords :
correlators; field programmable gate arrays; probability; FPGA; binary correlator; false alarm probability; hardware bit correlator; nondetection probability; Clocks; Correlators; Degradation; Field programmable gate arrays; Frequency synchronization; Hardware; Laboratories; Performance evaluation; Table lookup; Timing;
Journal_Title :
Communications Letters, IEEE
DOI :
10.1109/LCOMM.2007.070124