Functional latching devices for LSI

One important route to higher functional densities for LSI is through consolidation of more components within a given region. This paper repots on studies of integrated "latch" devices made by incorporating transistor flip-flops within a single isolation island and using the bulk resistivity of the epitaxial layer for resistive elements. Although most components are distinguishable, complex interaction makes a device approach to design and evaluation the most applicable technique. Principles of design and optimization are approached by a point-by-point analogy with the p-n-p-n switch. Comparable V-I plots are used to study effects of various parameters and geometries on stability and noise sensitivity. It is shown that a minimum bulk resistivity is required for positive latch-up at a given current and that "probe" contacts and buried layers at the output transistor also have a profound effect. Supporting experimental data are presented on switching characteristics as well. Several configurations have been fabricated and studied, with near counterparts in direct coupled as well as resistor, diode, transistor, and emitter-follower coupled circuits, plus several means of triggering them. Some counter applications will be described that are greatly simplified through this approach.