An elastic pipeline mechanism by self-timed circuits

Author

Komori, Shinji ; Takata, Hidehiro ; Tamura, Toshiyuki ; Asai, Fumiyasu ; Ohno, Takio ; Tomisawa, Osamu ; Yamasaki, Tetsuo ; Shima, Kenji ; Asada, Katsuhiko ; Terada, Hiroaki

Author_Institution

Mitsubishi Electr. Corp., Hyogo, Japan

Volume

23

Issue

1

fYear

1988

Firstpage

111

Lastpage

117

Abstract

An elastic pipeline mechanism that is especially suitable for data-driven processors is described. With the elastic pipeline scheme, a large processing rate and a smooth data stream in the pipeline are realized at the same time. Two types of self-timed circuits, which are used for data-transfer control circuits in the elastic pipeline, are proposed. Using different types of transfer control circuits, two loop-shaped elastic pipeline mechanisms have been implemented on test chips and are compared with each other. One of these chips demonstrated that the data throughput in the pipeline was 55 megawords per second and that the critical path within a pipeline stage corresponded to 16 inverter delays. This indicates the possibility of high-performance data-driven processors.<>

Keywords

VLSI; integrated logic circuits; parallel architectures; pipeline processing; VLSI; data-driven processors; data-transfer control circuits; elastic pipeline mechanism; logic circuits; loop shaped mechanisms; self-timed circuits; Circuit testing; Clocks; Delay; Distributed control; Integrated circuit interconnections; Inverters; Laboratories; Pipelines; Throughput;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.266

Filename

266