Probabilistic compaction algorithm for LSI cell layout design

A compaction algorithm is presented that compacts LSI cell layout in a probabilistic manner. The algorithm is based on the constraint graph where the edge length is iteratively changed probabilistically using parameters and random numbers. Some experimental results show that an area reduction of from 2% to 20% can be achieved in comparison with the conventional compaction algorithm. The algorithm can also control the aspect ratio of the compacted layout.