Author_Institution :
Technical University of ¿ód¿, Institude of Physics,, ¿ód¿, Poland
Keywords :
CMOS integrated circuits; NAND circuits; digital simulation; integrated circuit technology; integrated logic circuits; invertors; logic gates; semiconductor device models; 25 to 250 C; 4 micron; CMOS logic cell switching speed; NAND gates; SPICE2G.6 simulations; average gate delay; capacitively loaded inverters; delineation factor; gate propagation delay; high temperature operation; junction temperature; temperature dependence; thermal characterisation;
