DocumentCode
1032215
Title
Mapping iterative networks to parallel lookahead circuits
Author
Shyur, J.-C. ; Parng, T.-M.
Author_Institution
Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei
Volume
30
Issue
3
fYear
1994
fDate
2/3/1994 12:00:00 AM
Firstpage
202
Lastpage
203
Abstract
Finite state machines have sequential iterative network implementations. The authors show that by the proposed algorithm and Boolean matrix operations, nonlinear parts of recurrence sequences can be eliminated. Linear mapping is thus obtained, which by use of the prefix technique, results in parallel lookahead circuits
Keywords
carry logic; finite state machines; sequential machines; Boolean matrix operations; finite state machines; linear mapping; parallel lookahead circuits; prefix technique; recurrence sequences; sequential iterative network implementations;
fLanguage
English
Journal_Title
Electronics Letters
Publisher
iet
ISSN
0013-5194
Type
jour
DOI
10.1049/el:19940165
Filename
267244
Link To Document